1. Field of the Invention
The present invention relates to a method for reducing static power dissipation in a semiconductor device, and more particularly to a method for reducing static power dissipation in a semiconductor device by turning off a power supply voltage when the device is during a sleep mode.
2. Description of the Prior Art
The metal-oxide-semiconductor (MOS) transistor is a primary device formed in a semiconductor substrate, as shown in FIG. 1, a N type MOS transistor 12 formed on P type substrate 10. In general, a power voltage Vcc is supplied to the drain 14 of the NMOS transistor 12, and the source 16 of the NMOS transistor 12 is grounded. When a voltage larger than the threshold voltage Vth is supplied to the gate of the NMOS transistor 12, the NMOS transistor 12 is turned on, and then there is electrical conductance between the drain 14 and the source 16. That is, a current flow occurs from the drain 14 to the source 16. However, referring to FIG. 1, even though the NMOS transistor 12 is turned off, due to the gate voltage less than Vth, the drain voltage Vcc also induce some kinds of leakage paths. For example, the possible leakage paths can be subthreshold current, the direct oxide tunneling current I11, the drain-induced barrier lowering current (DIBL) I12, and the drain to substrate p-n junction current I13. All of the leakage paths induced by the drain voltage generate static power dissipation Ileakagexc3x97VDD when the NMOS transistor 12 is during a sleep mode.
Traditionally, the measure to reduce the static power dissipation of the semiconductor device is by way of eliminating/or blocking the leakage paths. For example, utilizing a high-K material to increase the thickness of the gate isolating layer to reduce the tunneling current of the gate isolating layer, and using the substrate back bias to control the subthreshold leakage. Most of the traditional measures use the process technique and/or control circuit to reduce the leakage currents. Therefore, the present invention provides a new concept to decrease the static power dissipation from a voltage source Vcc.
It is one object of the present invention to provide a method for reducing static power dissipation in a semiconductor device, in which a simple control device is used to connect with the semiconductor device through an output terminal of the control device, and serving for a power voltage supply controller. During a sleep mode of the semiconductor device, the output terminal of the control device is grounded and thus there is no power voltage supplied to the semiconductor device. Thereby, the static power dissipation of the semiconductor device is reduced by way of turning off the power voltage supply during the sleep mode.
It is another object of the present invention to provide a method for reducing static power dissipation in a semiconductor device, in which a control device having two input terminals and one output terminal is provided. One of the two input terminals is connected with a voltage supply, the other of the two input terminals is connected with a control signal. The output terminal of the control device is connected to a drain of a MOS transistor. When the MOS transistor is in sleep mode, the control signal is activated and the output terminal is grounded, and thus the drain is grounded. And then, all of the possible leakage paths induced by the drain voltage are inhibited, which contribute to the static power dissipation of the MOS transistor. Therefore, the static power dissipation of the MOS transistor during non-working state is eliminated by this means.
In order to achieve the above objects, the present invention provides a method for reducing static power dissipation in a semiconductor device, in which a control device having two input terminals and one output terminal is provided. One of the two input terminals is connected with a voltage supply, the other of the input terminals is connected with a control signal. The output terminal of the control device is connected to a drain of a metal-oxide-semiconductor (MOS) device. When the control signal is activated, the output terminal of the control device is grounded and thus the drain of the MOS device is grounded. Thereby, all of the possible leakage paths induced by the drain voltage are inhibited. When the control signal is un-activated, the output terminal of the control device provides a supply voltage to the drain of the MOS device, and then the MOS device is in a normal state. While, the static power dissipation of the MOS device, contributed from the leakage paths induced by the drain voltage, is reduced, by turning off the drain voltage supply during a sleep mode of the MOS device.